The present invention relates to a serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory and more particularly to the transfer of data from the parallel shift registers to the serial output shift register of such a memory.
In a certain type of serial to parallel to serial charge coupled device shift register memory, two groupings of sequentially ordered bits are interlaced when they are fed into the parallel shift registers of the memory and as a result are not arranged sequentially when they reach the outputs of those parallel shift registers for shifting out of the memory through the serial output register of the memory. In the Kosonocky et al U.S. Pat. No. 3,967,254, sorting stages are inserted between the end of the parallel shift registers and the serial output shift registers to place the interlaced data back into its original groupings of sequentially ordered bits and then to transfer these groupings one at a time to the output shift register so that the bits then emerge from the output shift register a grouping at a time in ascending sequential order.
The sorting stages in the mentioned Kosonocky et al patent have two interdigitated electrodes. Each electrode has fingers that shield the last stage of a different set of the parallel shift registers from potentials applied by one of two transfer electrodes overlying the interdigitated electrodes. By first applying a transfer pulse to one of the transfer electrodes and then at a different time to the other of the transfer electrodes, data bits making up one of the original groupings can be transferred to the output shift register at a different time than data bits from the other of the original groupings. Still another transfer pulse is applied to a third transfer electrode to synchronize the transfer of the separated groupings to the output shift register for the SPS device.